Physical Modeling and System Level Performance Characterization of a Protocol Processor Architecture

This article presents a method for estimating and optimizing a customizable system level architecture in the early phase of design. The model has been implemented in MATLAB. The methodology is interconnect centric and the worst case wire path has been used for calculating the overall delay of the logic. The system has been divided into different architectural blocks and the modeling method of each block depends on their primary function in the physical system performance. The developed model has been tested on a TTA protocol processor architecture designed for processing ATM AIS cells. The results have been presented for two different architectures and the effect of technology scaling on the system performance has also been examined.